As semiconductor devices are increasingly integrated various problems may arise that can degrade transistor characteristics. For example, as the channel length of a field effect transistor becomes shorter, short channel effects such as punch-through, drain induced barrier lowering (DIBL), subthreshold swing and leakage current increase, or the like, may arise.
To potentially overcome the above problems, many studies have been done for fabricating three-dimensional devices. In particular, dual gate transistor or FinFET technology has been suggested.
The FinFET technology may be categorized as two classes: using a silicon-on-insulator (SOI) substrate and using a bulk silicon substrate. A method of manufacturing a FinFET using an SOI substrate is disclosed in U.S. Pat. No. 6,413,802, and a method of manufacturing a FinFET using a bulk silicon substrate is disclosed in U.S. Pat. No. 5,844,278. The FinFETs disclosed in these patents use polysilicon as gate electrode material. Such a FinFET using a polysilicon gate may encounter problems caused by RC delay.
Bin Yu et al. discloses a FinFET with a gate stacked with a polysilicon and a silicide thereon in a paper entitled “FinFET Scaling to 10 nm Gate Length,” International Electron Devices Meeting (IEDM), Dec. 8-11, 2002, pages 251-254. As disclosed in the paper, an SOI substrate is etched to form a silicon fin. A polysilicon layer is formed to cross the silicon fin (on and lateral sides of the silicon fin). A nickel silicide layer is formed on the polysilicon layer to form a stack gate electrode.
Jakub Kedzierski et al. proposed a method for fully siliciding polysilicon, in a paper entitled “Metal-gate FinFET and Fully-Depleted SOI Devices Using Total Gate Silicidation,” International Electron Devices Meeting (IEDM), Dec. 8-11, 2002, pages 247-250. As disclosed in the paper, a nickel silicide gate is formed to cross a silicon fin.